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HARDWARE IMPLEMENTATION OF VIDEO PROCESSING DEVICE USING RESIDUE NUMBER SYSTEM

https://doi.org/10.37493/2307-910X.2021.1.2

Abstract

This paper considers the creation of video signal processing device. Important performance criteria of these devices are speed and power consumption. We used an Alinx AX309 board containing FPGA Xilinx Spartan6-xc6slx9 as a hardware basis for the implementation of the system. OV7670 video camera was used to obtain a video signal. The output of the processed video was carried out on the Alinx AN430 LCD display and on the standard VGA port. We used the Residue Number System to accelerate calculations. It allowed to improve device speed by 28% compared to using traditional two's complement number system.

About the Authors

P. A. Lyakhov
North-Caucasus Federal University
Russian Federation


A. S. Ionisyan
North-Caucasus Federal University
Russian Federation


V. V. Masaeva
North-Caucasus Federal University
Russian Federation


M. V. Valueva
North-Caucasus Federal University
Russian Federation


References

1. Акушский, И. Я. Машинная арифметика в остаточных классах / И. Я. Акушский, Д. И. Юдицкий. - М. : Сов. Радио, 1968. - 440 с.

2. Червяков Н.И. Методы, алгоритмы и техническая реализация основных проблемных операций, выполняемых в системе остаточных классов // Инфокоммуникационные технологии. -№4, 2011.-C.4-12.

3. Abeydeera M., Karunaratne M., Karunaratne G. and Silva K. "4K Real- Time HEVC Decoder on an FPGA," IEEE Transactions on circuirs and systems for video technology, Vol. 26, No. 1, January 2016.

4. Bovik Al. 'Handbook of image and video processing," Texas: Elsevier, 2005, 1372 p.

5. Cardarilli G.C., Nannarelli A. and Re M. "Residue number system for low-power DSP applications," Proc. 41st Asilomar Conf. Signals, Syst., Comput, 2007, pp. 1412-1416.

6. Chervyakov N.I., Molahosseini A.S., Lyakhov P.A., Babenko M.G. and Deryabin M.A. "Residue-to binary conversion for general moduli sets based on approximate Chinese remainder theorem," International journal of computer mathematics, Vol. 94, No. 9, pp. 18331849, 2017.

7. Gonzalez R.C., Woods R.E. and Eddins S.L. "Digital Image Processing Using MATLAB," Pearson Prentice Hall, 2003, 609 P.

8. Kao Ch.-Ch., Lai J.-H. and Chien Sh.-Y. "VLSI Architecture Design of Guided Filter for 30 Frames/s Full-HD Video," IEEE Transactions on circuits and systems for video technology, Vol. 24, No. 3, March 2014.

9. Loques O.G. and Kramer J. "Flexible fault tolerance for distributed computer systems," in IEE Proceedings E - Computers and Digital Techniques, vol. 133, no. 6, pp. 319-332, November 1986.

10. Pratt W.K. "Digital Image Processing," Wiley-Interscience; 4 edition, 2007, 812 P.

11. Vasalos E., Bakalis D. and Vergos H.T. "RNS Assisted Image Filtering and Edge Detection, Digital Signal Processing (DSP)," 2013 18th International Conference on, 1-3 July 2013, pp. 1-6.

12. Zhang X., Sun H., Chen Sh. and Zheng N. "VLSI Architectuer Exploration of Guided Image Filtering for 1080P@60Hz Video Processing," IEEE Transactions on circuirs and systems for video technology, Vol. 28, No. 1, January 2018.

13. https://github.com/anserion/ov7670_filter_rns дата обращения 12.10.2020).


Review

For citations:


Lyakhov P.A., Ionisyan A.S., Masaeva V.V., Valueva M.V. HARDWARE IMPLEMENTATION OF VIDEO PROCESSING DEVICE USING RESIDUE NUMBER SYSTEM. Modern Science and Innovations. 2021;(1):15-21. (In Russ.) https://doi.org/10.37493/2307-910X.2021.1.2

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ISSN 2307-910X (Print)